Differential timing transfer over synchronous ethernet using digital frequency generators and control word signaling

ABSTRACT

A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

CROSS-REFERENCE TO RELATED APPLICATION

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STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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FIELD OF THE INVENTION

The present invention relates generally to a method and system fordifferential timing transfer in communication networks and morespecifically to a method and system for differential timing transferover Synchronous Ethernet using digital frequency generators and controlword signaling.

BACKGROUND OF THE INVENTION

Differential timing transfer is used when there is a network interfacewith its own source clock and there is the need to transfer this clockover a core packet network (with its own independent network-widereference clock) to another interface. This transfer is performed whileeach interface and the core network maintain their timing traceabilityto their independent source clocks.

Differential clocking, such as the Synchronous Residual Time Stamp(“SRTS”) method specified for Asynchronous Transfer Mode (“ATM”)networks, allows equipment at the edges of a packet network to use aclocking signal that is different and completely independent from theclocking signal being used in the core packet network. The Residual TimeStamp (“RTS”) measures the difference between the service clock receivedon a Time Division Multiplexing (“TDM”) interface and the network-widereference clock. Stringent protocol requirements of SRTS require thatthe RTS value be specified using four bits and must be sent per eightcells using one bit in the ATM Adaptation Layer 1 (“AAL1”) header forevery odd sequence numbered cell. The RTS is propagated to the remoteend of the circuit in the AAL1 header of the ATM cell. The receiving endreconstructs the clock by adjusting the reference clock by the RTSvalue.

Adaptive clock recovery (“ACR”) is another technique used to distributeand recover clock from a packet network. The task of clock recovery isan “averaging” process that mitigates the deleterious effects of networkimpairments, such as random packet delay variation (“PDV”), and capturesthe average rate of transmission of the original bit stream. In adaptiveclock recovery, because there is no network-wide reference clockavailable, the performance of ACR techniques are subject to packetnetwork impairments and cannot be guaranteed. For high performance,adaptive clock recovery requires that the slave implement verysophisticated phase locked loops and highly expensive oscillators.

Synchronous Ethernet network synchronization is a recently developedtechnology used to extend the well-known concepts of TDM networksynchronization into the domain of packet-based networks, which untilnow have been specified as asynchronous in nature. The timing standardfor Synchronous Ethernet implementations has been defined by theTelecommunication Standardization Sector of the InternationalTelecommunication Union (“ITU-T”), in recommendation G.8261, entitled“Timing and Synchronization Aspects in Packet Networks.” SynchronousEthernet provides frequency distribution via the Ethernet physicallayer. Synchronous Ethernet is essentially native Ethernet equipped withtiming traceability at the physical layer.

For traditional Ethernet networks, the timing sources at each edge ofthe network cannot be synchronized to each other. Therefore, what isneeded is a simple, accurate, and inexpensive system and method forproviding differential timing transfer over Synchronous Ethernetnetworks.

SUMMARY OF THE INVENTION

The present invention advantageously provides a method, system andmaster service interface for transferring differential timing over apacket network. Generally, the master service interface creates acontrol signal that is used to synthesize a copy of a service clockconnected to the master service interface, as well as to recover orrecreate the service clock at a remote receiving, or “slave” serviceinterface.

In accordance with one aspect of the present invention, a method isprovided for transferring differential timing over a packet network. Thepacket network includes a service clock connected to a transmittingservice interface, which in turn is coupled to a receiving serviceinterface through a network backplane. A primary reference clock isprovided to time the network backplane. The primary reference clock isused to synthesize a copy of the service clock connected to thetransmitting service interface. A first control word is generated whichcontains an error differential between the service clock and thesynthesized copy of the service clock. A packet containing the firstcontrol word is transmitted through the network backplane to thereceiving service interface. The first control word is used to recreatethe service clock for timing the receiving service interface.

In accordance with another aspect of the present invention, a system fortransferring differential timing over a packet network includes anetwork backplane, a transmitting service interface, and a receivingservice interface. The network backplane is timed by a primary referenceclock and is communicatively coupled to the transmitting serviceinterface and to the receiving service interface. Using the primaryreference clock, the transmitting service interface operates tosynthesize a copy of a service clock connected to the transmittingservice interface. The transmitting service interface further operatesto generate a first control word which contains an error differentialbetween the service clock and the synthesized copy of the service clock,and to transmit a packet containing the first control word through thenetwork backplane to the receiving service interface. The receivingservice interface operates to receive the first control word and use thefirst control word to recreate the service clock for timing thereceiving service interface.

In accordance with yet another aspect of the present invention, a masterservice interface for transferring differential timing over a packetnetwork includes a master clock and a processor. The packet network istimed by a primary reference clock. The master clock operates tosynthesize a copy of a service clock connected to the master serviceinterface; and generate a control word containing an error differentialbetween the service clock and the synthesized copy of the service clock.The processor is communicatively coupled to the master clock. Theprocessor operates to transmit a packet containing the control wordthrough the packet network.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present invention, and theattendant advantages and features thereof, will be more readilyunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram of an exemplary packet data communicationsystem using differential clocking, constructed in accordance with theprinciples of the present invention;

FIG. 2 is a block diagram of an exemplary Synchronous Ethernet systemconstructed in accordance with the principles of the present invention;

FIG. 3 is a block diagram of an exemplary differential clocking schemeconstructed in accordance with the principles of the present invention;

FIG. 4 is a block diagram of an exemplary master clock configured as adigital phase-locked loop constructed in accordance with the principlesof the present invention;

FIG. 5 is a block diagram of an exemplary master clock operating in afree-running mode constructed in accordance with the principles of thepresent invention;

FIG. 6 is a block diagram of an exemplary slave clock constructed inaccordance with the principles of the present invention;

FIG. 7 is a flow diagram illustrating communicating control words frommaster to slave clock constructed in accordance with the principles ofthe present invention;

FIG. 8 is a flow diagram illustrating a process for mapping a mastercontrol word to a slave control word when the master and slave digitaloscillators are dissimilar, constructed in accordance with theprinciples of the present invention;

FIG. 9 is a block diagram of an exemplary phase-frequency detectorconstructed in accordance with the principles of the present invention;

FIG. 10 is a timing diagram illustrating the operation of an exemplaryphase-frequency detector when the service clock leads the digitaloscillator output according to the principles of the present invention;

FIG. 11 is a timing diagram illustrating the operation of an exemplaryphase-frequency detector when the service clock lags the digitaloscillator output according to the principles of the present invention;

FIG. 12 is a timing diagram illustrating the operation of an exemplaryphase-frequency detector when the service clock is in phase with thedigital oscillator output according to the principles of the presentinvention;

FIG. 13 is a state diagram for an exemplary phase-frequency detectoraccording to the principles of the present invention;

FIG. 14 is a graph illustrating the characteristics of an exemplaryphase-frequency detector as a function of counter output, C, versusphase error, θ_(e), in accordance with the principles of the presentinvention;

FIG. 15 is a timing diagram illustrating error patterns of aphase-frequency detector constructed in accordance with the principlesof the present invention;

FIG. 16 is a flow diagram illustrating dividing the service clock andthe digital oscillator output down to lower frame rates in accordancewith the principles of the present invention;

FIG. 17 is a timing diagram illustrating initial misalignment phaseerror at a phase-frequency detector in accordance with the principles ofthe present invention;

FIG. 18 a block diagram of an exemplary Direct Digital Synthesizer(“DDS”) constructed in accordance with the principles of the presentinvention;

FIG. 19 is a block diagram of an exemplary Divide-by-N counteroscillator (“DNCO”) constructed in accordance with the principles of thepresent invention;

FIG. 20 is a timing diagram illustrating the operation of a DNCO inaccordance with the principles of the present invention;

FIG. 21 is an alternative implementation of a DNCO, constructed inaccordance with the principles of the present invention;

FIG. 22 is a control diagram of an exemplary digital phase locked loopconstructed in accordance with the principles of the present invention;and

FIG. 23 is a more detailed control diagram of the exemplary digitalphase locked loop of FIG. 22 constructed in accordance with theprinciples of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Before describing in detail exemplary embodiments that are in accordancewith the present invention, it is noted that the embodiments resideprimarily in combinations of apparatus components and processing stepsrelated to implementing a system and method for providing differentialtiming transfer over a Synchronous Ethernet network. Accordingly, thesystem and method components have been represented where appropriate byconventional symbols in the drawings, showing only those specificdetails that are pertinent to understanding the embodiments of thepresent invention so as not to obscure the disclosure with details thatwill be readily apparent to those of ordinary skill in the art havingthe benefit of the description herein.

As used herein, relational terms, such as “first” and “second,” “top”and “bottom,” and the like, may be used solely to distinguish one entityor element from another entity or element without necessarily requiringor implying any physical or logical relationship or order between suchentities or elements.

One embodiment of the present invention advantageously provides a methodand system for providing differential timing transfer over a SynchronousEthernet network using digital frequency generators and control wordsignaling. According to one embodiment, a transmitter implements adigital phase-locked loop (“DPLL”) that consists of a phase-frequencydetector (“PFD”), a loop filter and a digital frequency generator, e.g.,a digital oscillator (“DO”). The transmitter periodically sends controlwords to the receiver so that the receiver may use these words to drivea local DO to reproduce the transmitter clock frequency.

Referring now to the drawing figures in which like reference designatorsrefer to like elements, there is shown in FIG. 1 an exemplary system 10for providing differential timing transfer across a packet network 12.The packet network 12 may be a Synchronous Ethernet network connectingtwo service interfaces 14, 16. The packet network 12 is synchronized toa primary reference clock 18, i.e., network clock f_(nc). The serviceinterfaces 14, 16 may be a private branch exchange (“PBX”), containingTime Division Multiplexing (“TDM”) equipment 20, 22 that each receivesits clocking from another reference source, e.g., a service clockf_(sc). Previously, in order to connect a service interface 14, 16 tothe packet network 12, the service clock had to be resynchronized withthe network clock 18. To avoid resynchronizing the service clock to thenetwork clock 18 in the course of TDM data transport through the packetnetwork 12, differential clock recovery allows the receiving serviceinterface 16, i.e., the “slave”, to recover the service clock f_(sc),from the transmitting interface 14, i.e., the “master”, using the commonnetwork clock 18 of the packet network 12 available both at thetransmitter 14 and receiver service interfaces 16.

A reference source timing signal is provided to the edge PBXs 14, 16independently from the packet network 12. Interworking functions (“IWF”)24, 26 provide an interface between the packet network 12 and each PBX14, 16. The IWFs 24, 26 are driven by the network clock 18. For PBX 14to send TDM data to a user at PBX 16, the differential clocking works asfollows. At PBX 14, TDM traffic is introduced into the packet network 12according to the timing determined by the service clock signal f_(sc).As IWF 24 segments the TDM bit stream 28 into packets 30 a, 30 b, 30 c,30 d, 30 e, 30 f (hereinafter referenced collectively as packet 30), IWF24 measures the difference between the service clock, which drives IWF24 and the network clock 18. As IWF 24 generates packets 30, itincorporates this time difference or residual time stamp (“RTS”) valueinto, for example, every eighth packet 30 c, 30 f. The packets 30 arepropagated through the packet network 12 to IWF 26. As IWF 26 receivesthe packets 30, it not only assembles the packets 30 into the originalTDM bit stream 28, but also reconstructs the user service clock timingsignal from the RTS value carried within every eighth packet. IWF 26reconstructs the clock by adjusting the network clock 18 by the RTS.Thus, using SRTS clocking, TDM traffic is synchronized between theingress (segmentation) side of the circuit emulation and the egress(reassembly) side of the circuit according to service clock signal,while the packet network continues to function according to the networkclock 18. Differential clocking method has better jitter and wanderperformance than adaptive clocking due to the use of common referencetiming 18 available at both ends of the packet network 12.

Traditional Ethernet, as defined according to the Institute ofElectrical and Electronics Engineers (“IEEE”) standard 802.3, isasynchronous. Thus, data is only transmitted when there is informationavailable to be transferred. The transmitted frames are preceded by apreamble designed to enable the receiver to lock onto the transmittingclock. Rather than maintaining global synchronization, each Ethernetreceiver locks onto the transmitter's timing on a frame-by-frame basis;thus, there is no need to maintain network-wide synchronization. Highlyaccurate synchronization is not as crucial as it is in TDM networksbecause received frames are buffered, so that small timing discrepanciesdo not lead to bit slips.

In keeping with Ethernet Standards requirements, the physical layertransmitter clock is derived from an inexpensive +/−100 ppm oscillatorand the receiver clock locks onto this clock. There is no need forlong-term frequency stability as the data is packetized and can bebuffered. For the same reason, there is no need for consistency betweenthe frequencies of different links.

The physical layer is not synchronous from a network operationsperspective. However, all the key elements exist within Ethernet to makeit synchronous and allow master-slave synchronization at the physicallayer and on a link-by-link basis. For example, as shown in FIG. 2 inrelation to a Synchronous Ethernet network 31, the clock 32 for thephysical layers 34 of the transmitter may be derived from a high qualityfrequency reference by replacing the local oscillator with a frequencysource traceable to a primary reference clock (“PRC”) 35. Thisenhancement does not affect the operation of any of the Ethernet upperlayers 36 which are oblivious to the change. The receiver at the otherend of the link automatically locks onto the clock 38 of the physicallayer 40 of the received signal, and thus itself gains access to ahighly accurate and stable frequency reference. Again, the operation ofthe Ethernet upper layers 42 of the received signal is not affected.Thus, Synchronous Ethernet may distribute timing via the Ethernetphysical layer. This process enables recovery of the physical layertiming, which may be used directly by locking downstream networks andapplications, or indirectly by using the physical layer timing as acommon reference.

Thus, the Ethernet physical layer signal is capable of being derivedfrom a primary reference clock as defined by the ITU-T G.811 standard.This clock can be extracted at the receiver, without requiring anychanges to the IEEE 802.3 model. In other words, Synchronous Ethernetdoes not violate the IEEE 802.3 model. By feeding one network element inan Ethernet network with a PRC, and employing Ethernet Physical layercircuitry with high quality oscillators, a fully timing synchronizednetwork may be established. Unlike TDM networks, this timing accuracy isnot required for the proper functioning of the data plane, which couldfunction perfectly well with relatively inaccurate and inconsistentphysical layer clocks. Instead, access to highly accurate and stablefrequency reference is provided to applications that require suchreferences.

For example, cellular communication base-stations require a highlyaccurate frequency reference from which they derive transmissionfrequencies and operational timing. Additionally, acceptance of TDMpseudowires is facilitated by accurate clock recovery.

Synchronous Ethernet may be used to lock up the clocks of a network butthere are times when an input source has it own independent clock (i.e.,the service clock) and cannot be locked to the Synchronous Ethernetclock (i.e., the network clock). In this case, the backbone SynchronousEthernet may be used for differential timing transfer. The advantage ofusing Synchronous Ethernet, as compared to sending timing information inpackets over an unlocked physical layer, is that Synchronous Ethernet isnot influenced by impairments introduced by the higher layers of thenetworking technology, e.g., packet loss, packet delay variation,out-order-arrival of packets. Hence, the frequency accuracy andstability may be expected to exceed those of networks withunsynchronized physical layers.

Referring now to FIG. 3, an exemplary embodiment of a packet network 44employing differential timing transference in accordance with theprinciples of the present invention is provided. The packet network 44includes a transmitter and a receiver communicating through a networkbackplane 31 such as, for example, a Synchronous Ethernet network. Thenetwork backplane 31 is clocked by a primary reference clock, e.g.,network clock 35. The network clock 35 frequency may be supplied from aglobal positioning system (“GPS”) or Building Integrated Timing Supply(“BITS”) and is assumed to drive both the master clock 46 and the slaveclock 56.

The transmitter has a master clock 46 consisting of a processor 47 and adigital phase-locked loop (“DPLL”) 48 with its own internal localdigital oscillator (“DO”) 50, phase-frequency detector (“PFD”) 52 andloop filter 54. The digital oscillator 50 is an active electronic devicethat accepts an input reference frequency and then generates one or morenew ones as commanded by a control word. In addition, the stability,accuracy, and spectral purity of the output correlate with theperformance of the input reference. Frequencies are generated as digitalrepresentations of the desired signal by means of digital samplingtechniques. The approach inherently affords great flexibility to thedesigner in terms of control and accuracy of the selected frequency.Since the DO chip contains the digital processing to construct andmanipulate a frequency, most analog circuitry is eliminated, along withbothersome analog tolerances and aging effects.

The function of the DO 50 is similar to that of a voltage controlledoscillator (“VCO”) in an analog phase locked loop (“PLL”). The VCOoutput frequency is a function of its input voltage, which isproportional to the phase error signal. In the digital PLL 48 with a DO50, the time period of the DO 50 is controlled directly. The output ofthe loop filter 54, in the form of a correction (or control) word 60, isused to control the period of the DO 50 in such a way as to decrease theerror signal generated by the phase detector. Two types of DOs, thedivide-by-N counter type oscillator (“DNCO”) and the direct digitalsynthesizer (“DDS”) are described in greater detail below.

The receiver includes a slave clock 56 which has a processor 57 and a DO58 and is located at another point in the packet network 44. DPLL errorsignals are generated by the PFD 52 of the master clock 46 and thenprocessed by the loop filter 54 to form a DO control word 60. The DOcontrol word 60 is used to control the local DO 50 in the master DPLL 48and also the slave DO 58. The control signals for the slave DO 50 arecommunicated across the packet network 44 from the master. Logically,the clock synchronization scheme can be viewed as having a single DPLLcontrolling many DOs. The local DO 50 of the master 46 acts as surrogateDO for the slave DO 58 from the point of view of locking onto thereference frequency.

Communication between the DPLL 48 of the master clock 46 and the DO 58of the slave clock 56 over the packet network 44 may be done in-band,i.e., clock state samples may be transmitted with or without user data,or out-of-band, i.e., using a separate physical or logical communicationchannel.

Since a network clock (f_(nc)) 35 is typically low-frequency and can bemuch lower than the PFD sampling frequency (f_(PFD)) and the DOhigh-speed internal clock (f_(DO)), the network clock 35 may be scaledto the appropriate frequency using scaling factor circuits 62, 64, 66.

An exemplary block diagram of the master clock 46 is provided in FIG. 4.The PFD 52 samples and compares the input reference signal f_(sc) withthe recovered (or synthesized) clock f_(T) to produce digitized errorsamples 68 which are proportional to the phase and frequency differencesbetween f_(sc) and f_(T). The error samples are filtered by a digitalloop filter 54 and corresponding output samples 70 are used to controlthe period of the DO 50. The output of the loop filter 54 is used tocorrect the phase and frequency of the DO 50 by changing the next clockperiod in an appropriate direction. A properly designed loop filter 54forces the reconstructed reference f_(T) to accurately track the inputreference signal f_(sc).

As noted above, because a network clock 35 is typical low-frequency andcan be much lower than the PFD sampling frequency and the DO high-speedinternal clock, the network clock 35 is scaled to the appropriatefrequency using the scaling factor circuits 62, 64.

The loop filter 54 output φ_(corr), or alternatively, the DO 50 input φ,is sampled periodically, e.g., at 1 to 20 Hz, and transmitted to theslave clock 56 to allow the slave clock 56 to emulate the state of themaster clock 46. It may be preferable to send φ_(corr) samples if anominal control word φ_(nom) 72 is known at the slave clock 56. φ_(corr)may also allow a fewer number of bits for transmission. In the casewhere φ_(nom) is known at the slave clock 56 but is not the same as thatof the master, then φ_(corr) is normalized accordingly.

FIG. 5 depicts the master clock 46 in a free-running mode. In this mode,the DO 50 is not synchronized with the incoming signal 74. The output ofthe loop filter 54 is disabled, e.g., set to zero, and the DO 50 isexcited by a pre-determined control input. The free-running mode may beused in point-to-point or point-to-multipoint applications wherefrequency traceability to other frequency domains is not required.

If the master clock 46 is extracting clocking reference from a line thatfails, the master can enter into a “holdover” mode. The “holdoverstability” is the amount of frequency offset that a clock experiencesafter it has lost its synchronization reference.

Referring to FIG. 6, an exemplary slave clock 56, constructed inaccordance with the principles of the present invention is shown. Thetime period of the DO 58 is controlled directly using the DO controlword 60 sent by the master 46. A full block diagram of the packetnetwork 44 employing differential timing transference, including detailsof the master clock 46 and the slave clock 56, is depicted in FIG. 7.Assuming, for example, that clock state samples, φ_(corr) or φ, are sentat a rate of 1 to 20 Hz. These samples are used to control the period ofthe DO 58 in such a way as to recover the service clock f_(sc). As notedearlier, the slave DO 58 is only a remote arm of the master clock 46,bridged by the packet backplane 31 and is excited with the same sequenceof control word 60 samples used at the master 46. If the master clock DO50 and slave clock DO 56 are assumed to be identical, then these twoclocks use the scaling factors for their respective DOs.

Although the above example assumes that the differential timingtechnique requires that the transmitter and receiver have similardigital oscillators (DO), the scheme may still be applied whendissimilar DO are used at the master and slave clocks. DOs arenumerically controlled oscillators which are typicallywell-characterized by mathematical mapping functions or lookup tablesrelating input control word and output frequency. With this attribute,the case of dissimilar DOs may be handled by simply mapping the derivedmaster DO control word into the appropriate slave DO control word beforeapplying this control word at the slave as illustrated in FIG. 8.

The idea of using a common network clock, transmitting the same controlword used at the master to the slave, and also the low samplingfrequency, makes the differential clocking scheme to be virtually freefrom the effects of control packet loss and delay variations. It is alsoimportant to note that at such low sampling rates, the quality of themaster clock would not be expected to have degraded between samplinginstances since oscillators used in TDM networks are expected to havewell defined frequency stability characteristics, i.e., variation infrequency per second. For example, the short term drift of a Stratum 3Clock system in holdover mode is less than 3.7×10⁻⁷ in 24 hours. This isequivalent to 0.37 ppm/day, or 0.57128 Hz/day. The drift of a Stratum 3EClock system with no input reference is less than 1×10⁻⁸ in 24 hours.The synchronized clock for one embodiment of the present invention mayhave a basic sampling interval of 0.4 s, enabling 32 phase detectorsamples to be accumulated for down-sampling and sent to the systemprocessor 47 for loop filter processing every 12.8 s. For the samereasons, loss of a control sample in the packet network would not causeclock degradation at the slave. From the above observations, theproposed clock synchronization scheme is expected to have strong jittersuppression characteristics.

Digital PFDs are commonly used to improve the pull-in range and pull-intime of phase-locked loop (“PLL”) circuits and are especially suited tofrequency-synthesis applications with periodic inputs. The digital PFDcircuit 52 can be implemented, for example, using D-type master-slaveflip-flops or R-S latches. FIG. 9 shows a PFD 52 built with two D-typeflip-flops 76, 78, an UP/DOWN counter 80 and an AND gate 84. The inputsUP and DOWN of the counter 80 respond only to the positive-going edgesof the inputs SC and DO. Therefore, the input duty cycles do not haveany effects on the outputs.

The basic architecture shown has a number of drawbacks, and as such,several variations of this basic architecture exist in practice. Forexample, the non-ideal behavior of the digital circuitry due to gatedelays alters the PFD 52 phase- and frequency-discriminatorcharacteristics significantly, thus limiting the maximum frequency ofoperation. Thus, this circuit is used to illustrate the ideal operatingprinciples of the PFD 52.

The operations of a typical PFD are illustrated in FIG. 10, FIG. 11, andFIG. 12. The frequency of the high-speed oscillator driving the UP/DOWNcounter 80 is usually f_(PFD)=M·f_(nom), where f_(nom) is the nominalfrequency of the service clock and M=Max is a large positive integer. Ifthe service clock frequency f_(sc) is greater than that of the DO outputf_(T), then the PFD 52 produces increasingly more positive pulses atoutput UP, while output DOWN remains at zero.

In FIG. 10, SC leads DO, hence the PFD 52 toggles between the states{UP=0, DOWN=0} and {UP=1, DOWN=0}. The time average value of thedifferential output, (UP−DOWN)_(AVE), measured by the high-speed counteris an indication of phase difference between the clock reference SC andDO output. The UP/DOWN counter 80 output also increases with time sincef_(sc)>f_(T). Thus, the counter output varies monotonically withfrequency error Δf=f_(sc)−f_(T) when the DPLL 48 is out of lock.Conversely, if f_(sc)<f_(T), then increasingly more negative pulsesappear at output DOWN, while UP is zero. In this case the PFD 52 togglesbetween the states {UP=0, DOWN=0} and {UP=0, DOWN=1}.

If but there is a phase difference between SC and DO, as indicated inFIG. 11, the circuit generates pulses at either UP or DOWN with a widthequal to the phase difference between the two inputs. When the twofrequencies are equal, one of the outputs has a duty cycle that is afunction of the difference between the input transition times while theother output remains inactive or low. Note that, in principle, UP andDOWN are never high simultaneously. Thus, the time average value of thedifferential output, (UP−DOWN)_(AVE), measured by the high-speedcounter, is an indication of phase difference between the clockreference SC and DO output. Since SC lags DO in FIG. 11, the PFD 52toggles between the states {UP=0, DOWN=0} and {UP=0, DOWN=1}. TheUP/DOWN counter also outputs a constant nonzero value with time.

Turning now to FIG. 12, assuming that the PFD 52 is in the {UP=0 andDOWN=0} state initially, if f_(sc)=f_(T) and there is zero phase errorbetween SC and DO, the SC and DO are exactly in phase, i.e., bothpositive edges of SC and DO occur at the same time, hence their effectscancel. The PFD 52 stays in the state {UP=0 and DOWN=0} forever. TheUP/DOWN counter 80 outputs a constant stream of zeros.

Assume, for example, that the service clock period is quantized by thehigh-speed clock with frequency f_(PFD)=1/τ_(PFD) into M=Max steps,i.e., Max=τ_(nom)/τ_(PFD). Note that the high-speed clock driving thePFD 52 may be different from that driving the DO 50. If the two clocksare equal, i.e., f_(PFD)=f_(DO), then Max=N_(nom). The UP-DOWN counter80 is a binary counter of certain size whose upper limit can be denotedas Max. The counter 80 operates at the speed or some multiple of thehigh-speed DO. The counter 80 counts up or down, initially from zero, atevery high-speed clock tick until it reaches Max−1, and then it willroll over and start again. The value stored in the counter 80 is latchedout by the active rising edge of the service clock SC. Therefore, whenthe DO is frequency locked to the service clock, the counter valueshould be a fixed number (see FIG. 11). The counter 80 should output thesame value at each active edge of SC after the DPLL 48 is locked.

FIG. 13 illustrates a state diagram 84 for the PFD 52. The PFD 52 can bein one of three states:

1. {UP=0, DOWN=0};

2. {UP=1, DOWN=0}; and

3. {UP=0, DOWN=1}.

However, there is a fourth state {UP=1, DOWN=1} that is inhibited by theaddition of the AND gate 82. Thus, whenever both flip-flops 76, 78 arein the 1 (high) state, a logic “high” level appears at their R (“reset”)inputs which resets both flip-flops 76, 78. Consequently the PFD 52 actsas a tri-state comparator (“triflop”).

The D-type flip-flops 76, 78 are triggered by the positive-going edgesof inputs, SC and DO, to the PFD 52. Initially, both outputs are low.When one of the PFD inputs rises, the corresponding output becomes high.The state of the finite-state machine (“FSM”) 84 moves from an initialstate to an UP or DOWN state. The state is held until the second inputgoes high, which in turn resets the circuit and returns the FSM to theinitial state.

It is important to note two observations from the waveforms shown inFIGS. 10-12. First, the UP/DOWN counter 80 attains its largest valuewhen the phase error is positive and approaches 2π. Second, the UP/DOWNcounter 80 attains its smallest value when the phase error is negativeand approaches −2π. Thus, if the counter output C is plotted against thephase error θ_(e), the resulting sawtooth function is shown in FIG. 14.This represents the characteristics curve 86 of the PFD 52 and coversphase errors greater than 2π or smaller than −2π. The curve is periodicwith period 2π. The PFD output is ideally linear for the entire range ofinput phase differences from −2π to 2 π radians and has maximum outputat Max.

The slope of the PFD characteristic curve 86 is equivalent to the gainof the PFD 52. From FIG. 14, the slope is given by

$\begin{matrix}{K_{PFD} = {\frac{Max}{2\pi}.}} & (1)\end{matrix}$

When the phase error is restricted to the range −2π<θ_(e)<2π, thecounter output becomes

$\begin{matrix}{{C\left( \theta_{e} \right)} = {{\frac{Max}{2\pi}\theta_{e}} = {K_{PFD}{\theta_{e}.}}}} & (2)\end{matrix}$

Referring back to FIG. 10, for instance, the SC is running faster thanthe DO. Thus, the time interval between the SC rising edge and the DOrising edge keeps increases as time progresses. When the PFD counter 80value reaches its maximum Max, assuming positive slope, or minimum −Max,assuming a negative slope, it starts back at 0, i.e., resets andincreases or decreases. Depending on the phase/frequency differencebetween SC and DO, the slope may be positive or negative and the slopebasically stays the same until the next reset.

To interface with the loop filter 54, the PFD 52 may be implemented asshown in FIG. 15. At each rising edge of SC, the PFD counter value C(n)is latched out. This value is converted to a phase error according tothe following expression:

${{{If}\mspace{14mu}{C(n)}} > {\frac{Max}{2}\mspace{11mu}{then}\mspace{14mu}{e(n)}}} = {{C(n)} - {Max}}$${{else}\mspace{14mu}{e(n)}} = {{{{{C(n)}.{If}}\mspace{14mu}{C(n)}} < {{- \frac{Max}{2}}\mspace{11mu}{then}\mspace{14mu}{e(n)}}} = {{C(n)} + {Max}}}$else  e(n) = C(n).e(n) is then passed to the loop filter 54 for processing.

In one embodiment, as shown in FIG. 16, to allow for the loop filter 54to be implemented in software on a processor, the inputs SC and DO maybe divided down to 8 KHz (or even 4 or 2 KHz) frame rates and fed to thePFD 52. Divide-by-X counters 88 a, 88 b are used in this case on the SCand DO clocks. For example, for T1 service clock, X may be 193, i.e.,equal to a T1 frame length, or multiple thereof. In which case, theinput frequencies to the PFD 52 are f₁=f_(sc)/X and f₂=f_(T)/X insteadof frequencies f_(sc) and f_(T). Denoting the scaled-down nominalfrequency as f_(temp)=f_(nom)/X, the maximum phase error isMax=f_(PFD)/f_(temp).

The input SC and DO frames are not necessarily aligned initially beforeentering the PFD 52. This initial misalignment would produce a staticphase error C_(s) at the PFD output which could be confused with agenuine phase error due to a true phase offset C_(offset) between SC andDO, as shown in FIG. 17. Additionally, with C_(offset) present, when theDO is frequency locked to the reference frequency, there is a constantphase error between them which can range between 0 and Max. This staticerror has to be determined and accounted for in all PFD outputs. Toremove this initial static phase error which is due to the initialmisalignment between the SC and DO frames, C_(offset) is determined atsystem startup or reset time, and subtracted from all PFD outputsincluding the initial PFD output, which is C_(offset). An alternativesolution is to align SC and DO at the frame level before entering thePFD 52.

Referring now to FIG. 18, a block diagram is provided which illustratesan exemplary embodiment of the master DO 50, implemented in the form ofa direct digital synthesizer 90 (“DDS”). The DDS 90 seemsarchitecturally simple, yet provides persuasive advantages that aredifficult or expensive to achieve with alternative synthesis methods.These advantages include very fast switching, fine steps, excellentphase noise, transient-free (phase continuous) frequency changes,frequency agility and extraordinary flexibility as a modulator, smallsize, among others.

Though there are many variations, the DDS 90 architecture may be viewedas an assembly comprised of only three common digital components: aphase accumulator 92 (or adder/accumulator), a mapping device such as aread-only-memory (“ROM”) 94 or random-access memory (“RAM”) (not shown),and a digital-to-analog converter (“DAC”) 96. In many cases a low-passfilter 98 is implemented at the output of the DAC 96 but this componentis not normally considered a part of the DDS 90. The high-speed clockmust operate at higher frequency than the synthesized clock because ofNyquist theorem.

The phase accumulator 92 generates the phase component of the outputclock f_(DDS). It is implemented as a q-bit adder 100, with two inputs:the phase increment word φ=D_(DDS) and the previous sum. The outputclock frequency can be expressed as

$\begin{matrix}{f_{DDS} = {\frac{\phi \cdot f_{o\; 2}}{2^{q}}.}} & (3)\end{matrix}$

The phase accumulator 92 represents a cyclic phase generator producing atime series of binary integer values (phase sequence) corresponding tothe oscillator progression of phase. The phase sequence is generated bya q-bit accumulator 102 clocked at the sample rate, f_(DO)=f_(o2), whichaccumulates, modulo 2^(q).

Once the phase information is generated, it must be converted to asinusoidal value. The lookup table 94 stores samples of a sinusoid. Thephase accumulator 92 is used to generate a suitable phase argument thatis mapped by the lookup table 94 to the desired output waveform. Thus,the second component in a DDS 90 is a memory or mapping device thatperforms the nonlinear transformation of wt

sin(wt). If an analog output is required, the DDS 90 presents thedigital samples from the lookup table 94 to a DAC 96 and a low-passfilter 98 to obtain an analog waveform with the specific frequencystructure. Resolution of the DAC 96 determines the quality of the outputwaveform. Of course, the samples are also commonly used directly in thedigital domain.

As an example, if the DDS 90 is operating with a control input φ=D_(nom)which corresponds to the nominal frequency f_(DDS)=f_(nom). Adding aquantity −D_(corr) to D_(nom) (i.e., D_(DDS)=D_(nom)−D_(corr)) resultsin a decrease in the output frequency, f_(DDS)=f_(nom)−Δf whereas addinga quantity +D_(corr) to D_(nom) (i.e., D_(DDS)=D_(nom)+D_(corr)) resultsin an increase in the output frequency, f_(DDS)=f_(nom)+Δf. Thus, byappropriately controlling the quantity D_(corr) added to D_(DDS), theoutput frequency of the DDS 90 (i.e., f_(DDS)) may be controlledaccordingly. The size of the phase increment determines the actualoutput frequency and the fixed binary width q of the accumulator 92(which overflows) determines the minimum frequency resolution of the DDS90.

Referring now to FIG. 19, an exemplary functional block diagram of analternative embodiment of a digital oscillator, a divide-by-N counteroscillator (“DNCO”) 104 is provided. This DNCO 104 behaves essentiallyas a programmable divide-by-N counter. The output of a stable high-speedoscillator is used to drive a counter 106 which increases by one everyclock cycle. The high-speed oscillator usually has a frequency,f_(DO)=f_(o3), equal to N_(nom) times the nominal frequency,f_(nom)=1/τ_(nom), where N_(nom) determines the number of quantizationlevels and the phase error resolution over 2π. The comparator 108compares the content of the counter 106 with the control input valueN_(DNCO) (control word 60) and when they match, outputs a pulse whichserves both as the DNCO output and a reset signal for the counter 106.Thus, the period of the counter output (the time between reset pulses)is proportional to N_(DNCO). By varying the control input N_(DNCO), theDNCO period may be controlled. The operation of the DNCO 104 isillustrated in FIG. 20. One can readily see from FIG. 20, theconvenience of generating timing pulses using the simple programmablecounter 106.

Another embodiment of a digital oscillator constructed using a DNCO 110is provided in FIG. 21. A countdown counter 112 is preset to countN_(DNCO) and counts down to zero. Upon hitting the zero state, an outputclock pulse is generated and the countdown counter 112 is reset toN_(DNCO) for the beginning of the next period. This approach may be morepreferable than the implementation shown in FIG. 19 with the up-counterbecause the delay in recognizing the zero state is constant for anycount.

Because a PLL is essentially a feedback control system, mathematicalmodels of the PLL components may be used in order to determine theparameters of the loop filter. Due to the discrete nature of the DPLL,its operations are described by linear difference equations. Thez-transform technique is employed to analyze the general tracking, i.e.,steady-state behavior of the DPLL. Under the steady-state assumption,the phase-frequency error samples are small and the general nonlineardifference equation may be approximated by a linear equation which maybe solved using the z-transform technique. It is noted that when theDPLL has acquired lock and is not pulled out by large phase steps,frequency steps, or phase noise applied to its reference input, itsperformance can be analyzed by a linear model.

In the DDS 90, the nominal control word 60 D_(nom) produces thecorresponding nominal frequency f_(nom). Assuming that the control inputD_(nom) is changed by the amount D_(corr) at discrete time n. Note thatchange takes effect in the next discrete interval. This change resultsin an output frequency of

$\begin{matrix}{{{f_{DDS}(n)} = {{\frac{f_{o\; 2}}{2^{q}}\left( {D_{nom} + {D_{corr}\left( {n - 1} \right)}} \right)} = {f_{nom} + {\Delta\;{f(n)}}}}},{or}} & (4) \\{{f_{DDS}(n)} = {f_{nom} + {\frac{f_{o\; 2}}{2^{q}}{{D_{corr}\left( {n - 1} \right)}.}}}} & (5)\end{matrix}$This corresponds to an angular frequency of

$\begin{matrix}{{\omega_{DDS}(n)} = {\omega_{nom} + {\frac{2\pi\; f_{o\; 2}}{2^{q}}{{D_{corr}\left( {n - 1} \right)}.}}}} & (6)\end{matrix}$

The above equation may also be written asω_(DDS)(n)=ω_(nom) +K _(DDS) D _(corr)(n−1)=ω_(nom)+Δω(n),  (7)where K_(DDS)=2πf_(o2)/2^(q) is the DDS gain. By definition, the phaseof the DDS θ_(DDS) is given by the integral over the frequency variationΔω(n)=ω_(DDS)(n)−ω_(nom) and is given as

$\begin{matrix}{{\theta_{DDS}(n)} = {{\sum\limits_{i = 0}^{n}{\Delta\;{\omega(i)}}} = {K_{DDS}{\sum\limits_{i = 0}^{n}{{D_{corr}(i)}.}}}}} & (8)\end{matrix}$

It is important to note that the DDS appears in the digital PLL as adigital integrator, just as the VCO appears as an analog integrator inthe analog PLL. Given that ω_(DDS)=2πf_(o2)D_(DDS)/2^(q), the DDS gaincan be obtained alternatively asK_(DDS)=dω_(DDS)/dD_(DDS)=2πf_(o2)2^(q). From the above integration, thetransfer function of the DDS in the z-domain is given as

$\begin{matrix}\begin{matrix}{{G_{DDS}(z)} = \frac{\Theta_{DO}(z)}{\Theta_{corr}(z)}} \\{= \frac{\Theta_{DDS}(z)}{D_{D}(z)}} \\{= {K_{DDS} \cdot \frac{z^{- 1}}{1 - z^{- 1}}}} \\{{= {2^{1 - q}\pi\;{f_{o\; 2} \cdot \frac{z^{- 1}}{1 - z^{- 1}}}}},}\end{matrix} & (9)\end{matrix}$where z⁻¹ denotes the delay operator (i.e., z⁻¹x(n)=x(n−1), andΘ_(DDS)(z) and D_(D)(z) are the z-transforms of θ_(DDS)(n) andD_(corr)(n), respectively.

The DNCO is a programmable oscillator, implemented by loading ahigh-speed counter with a variable count. Denoting τ=1/f_(nom) as thenominal, or center, period of the DPLL, the clock period, τ_(DNCO), ofthe DNCO may be expressed in terms of the clock period τ_(nom) asfollowsτ_(DNCO)(n)=τ_(nom)−Δτ(n−1),  (10)where Δτ(n−1) is the correction or control signal in the (n−1)thsampling instant. Note that τ_(nom) is the basic clock period, in theabsence of the correction signal, corresponding to a frequency ofω_(nom) rad/s. In the DPLL, the output of the loop filter is used tocontrol the period of the DNCO. If the high-frequency oscillator of theDNCO has a period equal to τ_(o3)=τ_(nom)/N_(nom), then the clock periodof the DNCO may be expressed in terms of the clock period τ_(o3) and thecorrection factor isτ_(DNCO)(n)=N _(nom)τ_(o3)−Δτ(n−1).  (11)

The error signal e(n) generated by the PFD 52 is processed by the loopfilter 54 (G_(lf)(z)) to obtain the correction factor N_(corr)(n). Fromthe operation of the DNCO, depending on the sign of N_(corr)(n), anumber of ticks of the high-speed clock τ_(o3)=1/f_(o3) are added to orsubtracted from the nominal number of ticks N_(nom). Thus, theexpression for the DNCO becomesτ_(DNCO)(n)=N _(nom)τ_(o3) −N _(corr)(n−1)τ_(o3),  (12)where Δτ(n−1)=N_(corr)(n−1)τ_(o3). Note that ω_(nom)=2π/τ_(o3)N_(nom).Let t(n) be the time corresponding to the beginning of the nth DNCOcycle and Δτ(n) as the DNCO input in the time interval [t(n),t(n+1)].Taking t(0) to be zero, it follows that

$\begin{matrix}\begin{matrix}{{t(n)} = {\sum\limits_{i = 1}^{n}{\tau_{DNCO}(i)}}} \\{= {{n\;\tau_{nom}} - {\tau_{o\; 3}{\sum\limits_{j = 1}^{n - 1}{N_{corr}(j)}}}}} \\{{= {{n\;\tau_{nom}} - {p(n)}}},}\end{matrix} & (13)\end{matrix}$where the time offset p(n) from the nominal time base nτ_(nom) is givenby

$\begin{matrix}{{p(n)} = {\tau_{o\; 3}{\sum\limits_{j = 1}^{n - 1}{{N_{corr}(j)}.}}}} & (14)\end{matrix}$The above summation is also equivalent to the integrationp(n)=p(n−1)+τ_(o3) N _(corr)(n−1).  (15)

With ω_(nom)τ_(nom)=2π being the nominal time or frequency base, theDNCO output phase changes in a linear manner at a rate proportional top(n) and may be expressed as the integratorω_(nom) p(n)=ω_(nom) p(n−1)+ω_(nom)τ_(o3) N _(corr)(n−1),  (16)orθ_(DNCO)(n)=θ_(DNCO)(n−1)+ω_(nom)τ_(o3) N _(corr)(n−1),  (17)where θ_(DNCO)(n)=ω_(nom) p(n) This expression is also equivalent to

$\begin{matrix}\begin{matrix}{{\theta_{DNCO}(n)} = {\omega_{nom}\tau_{o\; 3}{\sum\limits_{i = 0}^{n}{N_{corr}(i)}}}} \\{= {\frac{2\pi}{N_{nom}}{\sum\limits_{i = 0}^{n}{N_{corr}(i)}}}} \\{= {\frac{2\pi\; f_{nom}}{f_{o\; 3}}{\sum\limits_{i = 0}^{n}{{N_{corr}(i)}.}}}}\end{matrix} & (18)\end{matrix}$

Equations (17) and (18) form the basic model of the DNCO. Note that theDNCO appears in the DPLL as a digital integrator, just as the VCOappears as an analog integrator in an analog PLL. Thus, the gain of theDNCO from the above model is

$\begin{matrix}{K_{DNCO} = {K_{DO} = {\frac{2\pi}{N_{nom}}.}}} & (19)\end{matrix}$

The transfer function in the z-domain can also be obtained from theabove integrator as

$\begin{matrix}\begin{matrix}{{G_{DNCO}(z)} = \frac{\Theta_{DO}(z)}{\Theta_{corr}(z)}} \\{= \frac{\Theta_{DNCO}(z)}{N_{C}(z)}} \\{= {\omega_{nom}{\tau_{o\; 3} \cdot \frac{z^{- 1}}{1 - z^{- 1}}}}} \\{{= {\frac{2\pi}{N_{nom}} \cdot \frac{z^{- 1}}{1 - z^{- 1}}}},}\end{matrix} & (20)\end{matrix}$where z⁻¹ denotes the delay operator (i.e., z⁻¹x(n)=x(n−1)), Θ_(DNCO)(z)and N_(C)(z) are the z-transforms of θ_(DNCO)(n) and N_(corr)(n),respectively.

The PFD 52 measures the phase difference θ_(e)(n)=θ_(sc)(n)−θ_(DO)(n)between the DO clock phase θ_(DO)(n) and the service clock phaseθ_(sc)(n) and develops an output e(n) that is proportional to thisphase-frequency difference θ_(e)(n). The ranges of θ_(e)(n) and e(n) are−2π<θ_(e)(n)<2π and −Max<e(n)<Max, respectively. This operation can beexpressed ase(n)=K _(PFD)·θ_(e)(n),  (21)where, as shown in FIG. 14, the slope or gain K_(PFD)=Max/2π. The errorsignal output e(n) is passed to the loop filter 54, F(z), to beprocessed. The transfer function of the PFD 52 is given as

$\begin{matrix}{{{G_{PFD}(z)} = {\frac{E(z)}{\Theta_{e}(z)} = {K_{PFD} = \frac{Max}{2\pi}}}},} & (22)\end{matrix}$where E(z) and Θ_(e)(z) are the z-transforms of e(n) and θ_(e)(n),respectively.

The error signal e(n) from the PFD 52 is passed to a digital loop filter54, the output of which is used to adjust the frequency f_(DO) of theoscillator 50. There are many forms of filters that can be used as theloop filter 54. For example, the digital loop filter 54 may beimplemented as a proportional plus integral (“PI”) filter havingtransfer function G_(LF)(z) given by

$\begin{matrix}{{{G_{LF}(z)} = {\frac{\Theta_{corr}(z)}{E(z)} = {K_{1} + \frac{K_{2}}{1 - z^{- 1}}}}},} & (23)\end{matrix}$where K₁ and K₂ are the proportional and integral path gains,respectively. The loop filter being a PI filter yields a second-orderPLL.

The proportional gain K₁ and the integral gain K₂ determine the filterresponse. The filter gains K₁ and K₂ can be adjusted dynamically on thefly, with greater gain in the startup process for fast locking(acquisition mode) and smaller gain in steady-state for bettersteady-state error (tracking mode).

The PLL 48, with a well-designed loop filter 54, can eventuallyeliminate the phase difference and make the controlled oscillator outputphase and frequency lock to the reference. FIGS. 22 and 23 depict thePLL 48 as a closed-loop feedback control system. The system is asecond-order feedback system due to the first-order low-pass filter.

One embodiment of the present invention includes a method forsynthesizing a digital PLL 48 using control theory principles assumingthat the DPLL 48 is in a tracking (steady-state) mode with small phaseerror about the reference phase. The design is based on the digitizationof a continuous-time system whereby the s-plane poles and zeros of aspecified differential equation are mapped to the z-plane poles andzeros of a corresponding difference equation using a matched pole-zero(“MPZ”) method.

The analog or continuous-time PLL consists of a PFD, a loop filter andVCO. The PFD can simply be represented as a constant gain K_(PFD). TheVCO may be modeled as a perfect integrator in the Laplace domain asG_(VCO)(s)=K_(VCO)/s, where K_(VCO) is its gain. The loop filter can bespecified in Laplace domain as F(s). In the absence of noise, theclosed-loop transfer function and normalized phase error response arespecified in the Laplace domain, respectively, as

$\begin{matrix}{\begin{matrix}{{H(s)} = \frac{\Theta_{VCO}(s)}{\Theta_{sc}(s)}} \\{{= \frac{K_{PFD}K_{VCO}{F(s)}}{s + {K_{PFD}K_{VCO}{F(s)}}}},}\end{matrix}{and}} & (24) \\\begin{matrix}{\frac{\Theta_{e}(s)}{\Theta_{sc}(s)} = \frac{{\Theta_{sc}(s)} - {\Theta_{VCO}(s)}}{\Theta_{sc}(s)}} \\{= \frac{s}{s + {K_{PFD}K_{VCO}{F(s)}}}} \\{{= {1 - {H(s)}}},}\end{matrix} & (25)\end{matrix}$where Θ_(VCO)(s), Θ_(sc), and Θ_(e)(s) are the Laplace transforms of theVCP phase θ_(VCO)(t), service clock phase θ_(sc)(t), and phase errorθ_(e)(t), respectively.

The order of the loop is equal to the number of perfect integratorswithin the loop structure. Since the VCO is modeled as a perfectintegrator, the loop is at least of order 1. If the loop filter containsone perfect integrator, then the loop is of order 2.

The order of the loop can be shown to greatly influence the steady-stateperformance of the loop. The steady-state phase error can readily bedetermined from equation (25) by means of the final value theorem, i.e.,

$\begin{matrix}{{\lim\limits_{t\rightarrow\infty}{\theta_{e}(t)}} = {{\lim\limits_{s\rightarrow\infty}{s\;{\Theta_{e}(s)}}} = {\lim\limits_{s\rightarrow\infty}{\frac{s^{2}{\Theta_{sc}(s)}}{s + {K_{PFD}K_{VCO}{F(s)}}}.}}}} & (26)\end{matrix}$

Steady-state error is defined as the deviation of the VCO phase from thereference after the transient response has died out, which is simplyθ_(e)(∞). It can be shown by means of equation (26) that a first-orderloop or higher tracks an initial phase offset with zero steady-stateerror. Moreover, a second-order system is required to track a frequencystep, while a third-order loop must be employed to track an acceleratingphase with zero steady-state error.

Consider a second-order lag-lead filter (also known as aproportional-integral (“PI”) filter) which has transfer function

$\begin{matrix}{{F(s)} = {\frac{1 + {s\;\tau_{2}}}{s\;\tau_{1}}.}} & (27)\end{matrix}$where τ₁ and τ₂ are time constants of the filter. The filter has a poleat s=0 and therefore behaves like an integrator. It has (at leasttheoretically) infinite gain at zero frequency. The closed-loop transferfunction of the PLL with this filter is obtained as

$\begin{matrix}{{{H(s)} = {\frac{{2{\zeta\omega}_{n}s} + \omega_{n}^{2}}{s^{2} + {2{\zeta\omega}_{n}s} + \omega_{n}^{2}} = \frac{{2{\zeta\omega}_{n}s} + \omega_{n}^{2}}{\left( {s - s_{0}} \right)\left( {s - s_{1}} \right)}}},} & (28)\end{matrix}$where ω_(n) and ζ are the natural frequency and damping factors,respectively, and are specified in terms of K_(PFD), K_(VCO), τ₁ and τ₂as

$\begin{matrix}{{\omega_{n} = \sqrt{\frac{K_{PFD}K_{VCO}}{\tau_{1}}}},} & (29) \\{\zeta = {\frac{\omega_{n}\tau_{2}}{2}.}} & (30)\end{matrix}$These two parameters are used to specify performance requirements of asystem. The poles of the closed loop system ares _(0.1)=−ζω_(n) ±jω _(n)√{square root over (1−ζ²)}.  (31)When ζ>1, the poles are real; and when ζ<1, the poles are complex andconjugate. When ζ=1, the poles are repeated and real and the conditionis called critical damping. When ζ<1, the response is underdamped andthe poles are complex.

The transient response of the closed-loop system is increasinglyoscillatory as the poles approach the imaginary axis when ζ approacheszero. The above model can be directly applied to the PLL in thecontinuous-time domain. But for systems based on sampled data,discrete-time models are used.

A linearized, time-invariant, approximate transfer function for theentire DPLL can be derived based on the conditions that nonlinearity ofthe system quantization is neglected. The z-domain representation of thePFD 52, loop filter 54 and the controlled oscillator 50 are given,respectively, as

$\begin{matrix}{{{G_{PFD}(z)} = K_{PFD}},} & (32) \\{{{G_{LF}(z)} = {{K_{1} + \frac{K_{2}}{1 - z^{- 1}}} = \frac{{\left( {K_{1} + K_{2}} \right)z} - K_{1}}{z - 1}}},} & (33) \\{{G_{DO}(z)} = {\frac{K_{DO}z^{- 1}}{1 - z^{- 1}} = {\frac{K_{DO}}{z - 1}.}}} & (34)\end{matrix}$

Using these transfer functions, the closed-loop transfer function of theDPLL 48 becomes

$\begin{matrix}{{{H(z)} = \frac{{G_{PFD}(z)}{G_{LF}(z)}{G_{DO}(z)}}{1 + {{G_{PFD}(z)}{G_{LF}(z)}{G_{DO}(z)}}}},{or}} & (35) \\{{H(z)} = {\frac{{K_{PFD}{K_{DO}\left( {K_{1} + K_{2}} \right)}z} - {K_{PFD}K_{DO}K_{1}}}{z^{2} + {\left\lbrack {{K_{PFD}{K_{DO}\left( {K_{1} + K_{2}} \right)}} - 2} \right\rbrack z} - \left( {{K_{PFD}K_{DO}K_{1}} - 1} \right)}.}} & (36)\end{matrix}$

The MPZ method is now applied to the H(s) to obtain a discrete-timesystem H₂(z) that is of form (or relates to the discrete transferfunction) H(z). From this relationship, the closed form expressions forthe loop filter gains K₁ and K₂ are derived. The goal here is to map thesystem that meets the performance requirements specified by ω_(n) anddamping factor ζ to a corresponding model in the z-domain. The MPZmethod directly maps the s-plane poles and zeros of an analog system tothe corresponding z-plane poles and zeros of a discrete-time system.

An embodiment of the present invention uses a Modified-MPZ (“MMPZ”)method to convert the s-plane poles and zeroes to corresponding z-planepoles and zeroes for use in a discrete-time system. First, the s-planepoles and zeros are mapped into the z-plane using the relationship,z=e^(sT) ^(s) , where T_(s) is the sampling interval. The poles of H(s)at s=−ζω_(n)+jω_(n)√{square root over (1−ζ²)} map to a pole of H₂(z) ate^(T) ^(s) ^((−ζω) ^(n) ^(+jω) ^(n) ^(√){square root over (1−ζ ² )}⁾.The poles of H(s) at

s=−ζω_(n)−jω_(n)√{square root over (1−ζ²)} will map to a pole of H₂(z)at e^(T) ^(s) ^((−ζω) ^(n) ^(−jω) ^(n) ^(√){square root over (1−ζ ² )}⁾.The zero at s=−ω_(n)/2ζ maps to a zero of H₂(z) at e^(−ω) ^(n) ^(T) ^(s)^(/2ζ).

Second, a discrete-time transfer function is formed in z with the polesand zeroes determined above. Thus,

$\begin{matrix}{{{H_{2}(z)} = \frac{K_{D\; C}\left( {z - {\mathbb{e}}^{\omega_{n}{T_{s}/2}\zeta}} \right)}{\left( {z - {\mathbb{e}}^{T_{s}({{{- \omega_{n}}\zeta} + {{j\omega}_{n}\sqrt{1 - \zeta^{2}}}})}} \right)\left( {z - {\mathbb{e}}^{T_{s}({{{- \omega_{n}}\zeta} + {{j\omega}_{n}\sqrt{1 - \zeta^{2}}}})}} \right)}},} & (37)\end{matrix}$where K_(DC) is the DC or low-frequency gain of H₂(z).

Third, the DC or low-frequency gain of the discrete-time system H₂(z) isset equal to that of the continuous-time system H(s). The Final ValueTheorem is used to find the steady state value of a time function givenits Laplace transform or z-transform. For a function x(t), the theoremstates, in the s-domain, that

$\begin{matrix}{{{\lim\limits_{t\rightarrow\infty}{x(t)}} = {\lim\limits_{s\rightarrow 0}{{sX}(s)}}},} & (38)\end{matrix}$where X(s) is the Laplace transform of x(t), as long as all the poles ofsX(s) are in the left half-plane (“LHP”) of the s-plane. In thez-domain, the theorem states that

$\begin{matrix}{{{\lim\limits_{k\rightarrow\infty}{x\left( {kT}_{s} \right)}} = {\lim\limits_{z\rightarrow 1}{\left( {1 - z^{- 1}} \right){X(z)}}}},} & (39)\end{matrix}$where X(z) is the z-transform of x(t) and if all the poles of(1−z⁻¹)X(z) are inside the unit circle. The theorem can also be use tofind the DC gain of a system. The DC gain is the ratio of the output ofa system to inputs (presumed constant) after all transients havedecayed. To find the DC gain, it is assumed that there is a unit stepinput and the Final Value Theorem is used to compute the steady statevalue of the output. Therefore, for a system with transfer functionG(s), the DC gain is defined as

$\begin{matrix}{{{D\; C\mspace{14mu}{gain}} = {{\lim\limits_{s\rightarrow 0}{{{sG}(s)}\frac{1}{s}}} = {\lim\limits_{s\rightarrow 0}{G(s)}}}},} & (40)\end{matrix}$and for a system with transfer function G(z), the DC gain is defined as

$\begin{matrix}{{D\; C\mspace{14mu}{gain}} = {{\lim\limits_{z\rightarrow 1}{\left( {1 - z^{- 1}} \right){G(z)}\frac{1}{1 - z^{- 1}}}} = {\lim\limits_{z\rightarrow 1}{{G(z)}.}}}} & (41)\end{matrix}$

The DC gain of H(s) is obtained as

${\lim\limits_{s\rightarrow 0}{H(s)}} = 1.$Setting the DC gain of H₂(z) to that of H(s), it is easy to see thatK_(DC)=1. Therefore, the transfer function H₂(z) simplifies to

$\begin{matrix}{{H_{2}(z)} = {\frac{\left( {z - {\mathbb{e}}^{{- \omega_{n}}{T_{s}/2}\zeta}} \right)}{\left( {z - {\mathbb{e}}^{T_{s}({{{- \omega_{n}}\zeta} + {{j\omega}_{n}\sqrt{1 - \zeta^{2}}}})}} \right)\left( {z - {\mathbb{e}}^{T_{s}({{{- \omega_{n}}\zeta} + {{j\omega}_{n}\sqrt{1 - \zeta^{2}}}})}} \right)}.}} & (42)\end{matrix}$

The transfer function H₂(z) can further be expressed as

$\begin{matrix}{{H_{2}(z)} = {\frac{z - {\mathbb{e}}^{{- \omega_{n}}{T_{s}/2}\zeta}}{z^{2} - {2{\mathbb{e}}^{{- 2}{\zeta\omega}_{n}T_{s}}{\cos\left( {\omega_{n}T_{s}\sqrt{1 - \zeta^{2}}} \right)}z} + {\mathbb{e}}^{{- 2}{\zeta\omega}_{n}T_{s}}}.}} & (43)\end{matrix}$

Comparing the denominators (or characteristic functions) of H(z) andH₂(z), it is noted that

$\begin{matrix}{{{{{- K_{PFD}}K_{DO}K_{1}} + 1} = {\mathbb{e}}^{{- 2}{\zeta\omega}_{n}T_{s}}},{or}} & (44) \\{{K_{1} = {\frac{1}{K_{PFD}K_{DO}}\left\lbrack {1 - {\mathbb{e}}^{{- 2}{\zeta\omega}_{n}T_{s}}} \right\rbrack}},{and}} & (45) \\{{{{K_{PFD}{K_{DO}\left( {K_{1} + K_{2}} \right)}} - 2} = {{- 2}{\mathbb{e}}^{{- {\zeta\omega}_{n}}T_{s}}{\cos\left( {\omega_{n}T_{s}\sqrt{1 - \zeta^{2}}} \right)}}},{or}} & (46) \\{K_{2} = {{\frac{1}{K_{PFD}K_{DO}}\left\lbrack {1 + {\mathbb{e}}^{{- 2}{\zeta\omega}_{n}T_{s}} - {2{\mathbb{e}}^{{- {\zeta\omega}_{n}}T_{s}}{\cos\left( {\omega_{n}T_{s}\sqrt{1 - \zeta^{2}}} \right)}}} \right\rbrack}.}} & (47)\end{matrix}$

Typically, performance specification for feedback control systems ofteninvolves certain requirements associated with the time response of thesystem. The setting time, t_(set), is defined as the time it takes forthe system transients to decay. For the PLL, is also referred to as thelocking time. For the second-order system with 0≦ζ<1, the setting time(for the system to settle within 1% of the input amplitude) is given by

$\begin{matrix}{t_{set} = {\frac{4.6}{{\zeta\omega}_{n}}.}} & (48)\end{matrix}$

Thus, for a second-order system, by specifying the settling time,t_(set), and the damping factor (e.g., ζ=0.707), the undamped naturalfrequency ω_(n), and the filter gains K₁ and K₂ can easily be determinedfrom the above equations.

Embodiments of the present invention advantageously provide a method fordifferential timing transfer over Synchronous Ethernet networks. Theclock synchronization scheme includes a master DPLL with its own localDO, and a number of remote DOs placed at various locations in the packetnetwork. In the master, error signals are generated by a PFD and thenprocessed by a loop filter to form a DO control word. The DO controlword is used, in turn, to control the local DO as well as the remoteDOs. Communication between the master DPLL i.e., master clock, and theremote DOs, i.e., slave clocks, over the packet network may be donein-band (i.e., DO control words can be transmitted with or without userdata) or out-of-band (i.e., using a separate physical or logicalcommunication channel).

An exemplary method for designing the master DPLL 48 involvessynthesizing a DPLL from a specification for an analog PLL. The designis based on the digitization of a continuous-time system whereby thes-plane poles and zeros of a specified system are mapped to the z-planepoles and zeros of a corresponding discrete-time system using a modifiedMatched Pole-Zero (“MMPZ”) method.

The present invention can be realized in hardware, software, or acombination of hardware and software. Any kind of computing system, orother apparatus adapted for carrying out the methods described herein,is suited to perform the functions described herein.

A typical combination of hardware and software could be a specialized orgeneral purpose computer system having one or more processing elementsand a computer program stored on a storage medium that, when loaded andexecuted, controls the computer system such that it carries out themethods described herein. The present invention can also be embedded ina computer program product, which comprises all the features enablingthe implementation of the methods described herein, and which, whenloaded in a computing system is able to carry out these methods. Storagemedium refers to any volatile or non-volatile storage device.

Computer program or application in the present context means anyexpression, in any language, code or notation, of a set of instructionsintended to cause a system having an information processing capabilityto perform a particular function either directly or after either or bothof the following a) conversion to another language, code or notation; b)reproduction in a different material form.

In addition, unless mention was made above to the contrary, it should benoted that all of the accompanying drawings are not to scale.Significantly, this invention can be embodied in other specific formswithout departing from the spirit or essential attributes thereof, andaccordingly, reference should be had to the following claims, ratherthan to the foregoing specification, as indicating the scope of theinvention.

What is claimed is:
 1. A method for transferring differential timingover a packet network, the packet network having a transmitting serviceinterface coupled to a receiving service interface through a networkbackplane, the method comprising: providing a scaled primary referenceclock to time the network backplane; providing a service clock connectedto the transmitting service interface; generating a first control wordcontaining an error differential between the service clock and asynthesized copy of the service clock; inputting the first control wordto a digital oscillator, the digital oscillator providing thesynthesized copy of the service clock based on the first control word, atime period of the digital oscillator being controlled using at leastone clock state sampling; transmitting a packet containing the firstcontrol word through the network backplane to the receiving serviceinterface; and using the first control word and the scaled primaryreference clock to recreate the service clock for timing the receivingservice interface.
 2. The method of claim 1, wherein the networkbackplane operates using a Synchronous Ethernet protocol.
 3. The methodof claim 1, wherein a frequency of the primary reference clock issupplied by one of a global positioning system and a building integratedtiming supply.
 4. The method of claim 1, further comprising: updatingthe first control word at a periodic interval; transmitting a packetcontaining the updated control word to the receiving service interface;and applying the updated control word to the service clock timing thereceiving service interface.
 5. The method of claim 1, wherein thetransmitting service interface includes a digital phase-locked loop, thedigital phase-locked loop is synthesized from a specification for ananalog phase-locked loop based on the digitization of a continuous-timesystem to a corresponding discrete-time system using a modified matchedpole-zero method.
 6. The method of claim 5, wherein the modified matchedpole-zero method comprises: mapping s-plane poles and zeros of theanalog phase-locked loop into z-plane poles and zeros; forming adiscrete-time transfer function using the z-plane poles and zeroes; andsetting a low-frequency gain of the discrete-time system substantiallyequal to that of the continuous-time system.
 7. A method fortransferring differential timing over a packet network, the packetnetwork having a transmitting service interface coupled to a receivingservice interface through a network backplane, the method comprising:providing a primary reference clock to time the network backplane;providing a service clock connected to the transmitting serviceinterface; generating a first control word containing an errordifferential between the service clock and a synthesized copy of theservice clock; inputting the first control word to a digital oscillator,the digital oscillator providing the synthesized copy of the serviceclock based on the first control word; transmitting a packet containingthe first control word through the network backplane to the receivingservice interface; and using the first control word and the primaryreference clock to recreate the service clock for timing the receivingservice interface, wherein the transmitting service interface and thereceiving service interface have dissimilar digital oscillators, themethod further comprising mapping the first control word into a secondcontrol word usable by the digital oscillator of the receiving serviceinterface, the mapping based on a difference between the dissimilardigital oscillators.
 8. A system for transferring differential timingover a packet network, the system comprising: a network backplane timedby a scaled primary reference clock; a transmitting service interfacecommunicatively coupled to the network backplane, the transmittingservice interface connected to a service clock, the transmitting serviceinterface configured to: generate a first control word containing anerror differential between the service clock and a synthesized copy ofthe service clock; input the first control word to a master digitaloscillator, the master digital oscillator providing the synthesized copyof the service clock based on the first control word; and transmit apacket containing the first control word through the network backplane;and a receiving service interface communicatively coupled to the networkbackplane, the receiving service interface configured to: receive thefirst control word at a slave digital oscillator; and use the firstcontrol word and the scaled primary reference clock to recreate theservice clock for timing the receiving service interface.
 9. The systemof claim 8, wherein a frequency of the primary reference clock issupplied by one of a global positioning system and a building integratedtiming supply.
 10. The system of claim 8, wherein the transmittingservice interface is further configured to: update the first controlword at a periodic interval; and transmit a packet containing theupdated control word to the receiving service interface.
 11. The systemof claim 10, wherein the receiving service interface is furtherconfigured to apply the updated control word to the service clock timingthe receiving service interface.
 12. The system of claim 8, wherein thetransmitting service interface includes a digital phase-locked loop, thedigital phase-locked loop containing a phase-frequency detector, a loopfilter and a master digital oscillator; and the receiving serviceinterface includes a slave digital oscillator.
 13. The system of claim12, wherein the master digital oscillator is one of a direct digitalsynthesizer and a divide-by-N counter oscillator.
 14. The system ofclaim 13, wherein the first control word is used to control the masterdigital oscillator and the slave digital oscillator.
 15. The system ofclaim 12, wherein the digital phase-locked loop is synthesized from aspecification for an analog phase-locked loop based on the digitizationof a continuous-time system to a corresponding discrete-time systemusing a modified matched pole-zero method.
 16. The system of claim 15,wherein the modified matched pole-zero method comprises: mapping s-planepoles and zeros of the analog phase-locked loop into z-plane poles andzeros; forming a discrete-time transfer function using the z-plane polesand zeroes; and setting a low-frequency gain of the discrete-time systemequal to that of the continuous-time system.
 17. A system fortransferring differential timing over a packet network, the systemcomprising: a network backplane timed by a primary reference clock; atransmitting service interface communicatively coupled to the networkbackplane, the transmitting service interface connected to a serviceclock, the transmitting service interface configured to: generate afirst control word containing an error differential between the serviceclock and a synthesized copy of the service clock; input the firstcontrol word to a master digital oscillator, the master digitaloscillator providing the synthesized copy of the service clock based onthe first control word; and transmit a packet containing the firstcontrol word through the network backplane; and a receiving serviceinterface communicatively coupled to the network backplane, thereceiving service interface configured to: receive the first controlword at a slave digital oscillator; and use the first control word andthe primary reference clock to recreate the service clock for timing thereceiving service interface, wherein a nominal control word is known bythe receiving service interface, the first control word including atleast one sample of a correlation between the first control word and thenominal control word.
 18. A system for transferring differential timingover a packet network, the system comprising: a network backplane timedby a primary reference clock; a transmitting service interfacecommunicative) coupled to the network back lane the transmitting serviceinterface connected to a service clock, the transmitting serviceinterface configured to: generate a first control word containing anerror differential between the service clock and a synthesized copy ofthe service clock; input the first control word to a master digitaloscillator, the master digital oscillator providing the synthesized copyof the service clock based on the first control word; and transmit apacket containing the first control word through the network backplane;and a receiving service interface communicatively coupled to the networkbackplane, the receiving service interface configured to: receive thefirst control word at a slave digital oscillator; and use the firstcontrol word and the primary reference clock to recreate the serviceclock for timing the receiving service interface, wherein thetransmitting service interface and the receiving service interface havedissimilar master and slave digital oscillators, the receiving serviceinterface further operates to map the first control word into a secondcontrol word usable by the digital oscillator of the receiving serviceinterface, the mapping based on a difference between the dissimilardigital oscillators.
 19. A master service interface for transferringdifferential timing over a packet network, the packet network beingtimed by a primary reference clock, the master service interfacecomprising: a service clock configured to time the master serviceinterface; a master clock configured to: generate a control wordcontaining an error differential between the service clock and asynthesized copy of the service clock; and input the control word to adigital oscillator, the digital oscillator providing the synthesizedcopy of the service clock based on the first control word, a time periodof the digital oscillator being controlled using at least one clockstate sampling; and a processor communicatively coupled to the masterclock, the processor configured to transmit a packet containing thecontrol word through the packet network.
 20. The master serviceinterface of claim 19, wherein the processor is further configured to:update the control word at a periodic interval; and transmit a packetcontaining the updated control word to a slave service interface.